Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom. Accurate and\r\nrapid simulation tools are needed to explore the design space. To this aim, FPGA-based emulators have recently been proposed\r\nas an alternative to pure software cycle-accurate simulator. However, the advantages of on-hardware emulation are reduced by\r\nthe overhead of the RTL synthesis process that needs to be run for each configuration to be emulated. The work presented in\r\nthis paper aims at mitigating this overhead, exploiting a form of software-driven platform runtime reconfiguration. We present\r\na complete emulation toolchain that, given a set of candidate ASIP configurations, identifies and builds an overdimensioned\r\narchitecture capable of being reconfigured via software at runtime, emulating all the design space points under evaluation. The\r\napproach has been validated against two different case studies, a filtering kernel and an M-JPEG encoding kernel. Moreover, the\r\npresented emulation toolchain couples FPGA emulation with activity-based physical modeling to extract area and power/energy\r\nconsumption figures. We show how the adoption of the presented toolchain reduces significantly the design space exploration\r\ntime, while introducing an overhead lower than 10% for the FPGA resources and lower than 0.5% in terms of operating frequency.
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